一篇文章说明常见的AI芯片高速互连方案

创作时间:

作者:

@小白创作中心

一篇文章说明常见的AI芯片高速互连方案

引用

来源

https://www.scensmart.com/news/one-article-explains-common-high-speed-interconnect-solutions-for-ai-chips/

随着AI芯片技术的不断发展，高速互连方案成为了提升芯片性能的关键技术之一。本文将详细介绍NVIDIA的NV Link和NV Switch技术的发展历程及其性能参数，并对华为的NPU互连方案进行说明。

NVIDIA NV Link技术发展

产品	发布时间	显卡	连接数量	GPU 之间总带宽	应用架构
NV Link 1.0	2016	P100	4	160 GB/s	Pascal
NV Link 2.0	2017	V100	6	300 GB/s	Volta
NV Link 3.0	2020	A100	12	600 GB/s	Ampere
NV Link 4.0	2022	H100	18	900 GB/s	Hopper
NV Link 5.0	预计 2025	B200	18	1800 GB/s	Blackwell

华为NPU互连方案

npu-smi info -t topo
NPU0       NPU1       NPU2       NPU3       NPU4       NPU5       NPU6       NPU7       NPU8       NPU9       NPU10      NPU11      NPU12      NPU13      NPU14      NPU15      CPU Affinity
NPU0       X          HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       PIX        PHB        PHB        PHB        SYS        SYS        SYS        SYS        0-43,88-131
NPU1       HCCS       X          HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       PHB        PIX        PHB        PHB        SYS        SYS        SYS        SYS        0-43,88-131
NPU2       HCCS       HCCS       X          HCCS       HCCS       HCCS       HCCS       HCCS       PHB        PHB        PIX        PHB        SYS        SYS        SYS        SYS        0-43,88-131
NPU3       HCCS       HCCS       HCCS       X          HCCS       HCCS       HCCS       HCCS       PHB        PHB        PHB        PIX        SYS        SYS        SYS        SYS        0-43,88-131
NPU4       HCCS       HCCS       HCCS       HCCS       X          HCCS       HCCS       HCCS       SYS        SYS        SYS        SYS        PIX        PHB        PHB        PHB        44-87,132-175
NPU5       HCCS       HCCS       HCCS       HCCS       HCCS       X          HCCS       HCCS       SYS        SYS        SYS        SYS        PHB        PIX        PHB        PHB        44-87,132-175
NPU6       HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       X          HCCS       SYS        SYS        SYS        SYS        PHB        PHB        PIX        PHB        44-87,132-175
NPU7       HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       X          SYS        SYS        SYS        SYS        PHB        PHB        PHB        PIX        44-87,132-175
NPU8       PIX        PHB        PHB        PHB        SYS        SYS        SYS        SYS        X          HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       0-43,88-131
NPU9       PHB        PIX        PHB        PHB        SYS        SYS        SYS        SYS        HCCS       X          HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       0-43,88-131
NPU10      PHB        PHB        PIX        PHB        SYS        SYS        SYS        SYS        HCCS       HCCS       X          HCCS       HCCS       HCCS       HCCS       HCCS       0-43,88-131
NPU11      PHB        PHB        PHB        PIX        SYS        SYS        SYS        SYS        HCCS       HCCS       HCCS       X          HCCS       HCCS       HCCS       HCCS       0-43,88-131
NPU12      SYS        SYS        SYS        SYS        PIX        PHB        PHB        PHB        HCCS       HCCS       HCCS       HCCS       X          HCCS       HCCS       HCCS       44-87,132-175
NPU13      SYS        SYS        SYS        SYS        PHB        PIX        PHB        PHB        HCCS       HCCS       HCCS       HCCS       HCCS       X          HCCS       HCCS       44-87,132-175
NPU14      SYS        SYS        SYS        SYS        PHB        PHB        PIX        PHB        HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       X          HCCS       44-87,132-175
NPU15      SYS        SYS        SYS        SYS        PHB        PHB        PHB        PIX        HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       HCCS       X          44-87,132-175

Legend:
X=Self
SYS=Path traversing PCIe and NUMA nodes. Nodes are connected through SMP, such as QPI, UPI.
PHB=Path traversing PCIe and the PCIe host bridge of a CPU.
PIX=Path traversing a single PCIe switch
PXB=Path traversing multipul PCIe switches
HCCS=Connection traversing HCCS.
NA=Unknown relationship.